1. Field of the Invention
The present invention is directed to providing a failsafe time function in multiple systems in which different devices interact, where a standard time function that is available in the system is typically adjusted by a further independent timer, such as a monitoring timer or F-timer.
2. Description of the Related Art
The demands placed on the accuracy of the time signal are very high in the instances described, i.e., only a minimal fault and/or deviation tolerance is provided. The most well know counter is a timestamp counter (TSC), introduced with the x86 Pentium processors and since then featured in all CPU designs. This is a 64 bit register, the value of which is incremented with the CPU clock, and can also be read out from the kernel space and/or from the user space.
A second timer (i.e., an F-timer) hitherto had to be integrated to solve the problem of providing an accurate time signal. To this end, a corresponding hardware expansion, such as a special semiconductor module, is needed, which takes over the timing device.
It is also already known that an electrical oscillation can be generated to monitor a time base of a data processing unit by a single oscillating crystal and that a clock signal can be generated from the oscillation. As a result, a first task is cyclically called up with an interval from a first time duration and a counter value is changed to monitor the accuracy of a clock signal. In a second task, which is cyclically called up with an interval from a second time duration, an operation is applied to the counter value and a result of the operation is compared with a predeterminable limit value.
This timer monitoring function, however, does not provide an acceptable level of reliability, i.e., the function fails to meet the requirements set forth in the corresponding standards, e.g., International Electrotechnical Commission Standard (IEC) 61508.